#ifndef REG_RCC_TYPE_H_
#define REG_RCC_TYPE_H_
#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

typedef struct
{
    volatile uint32_t CK;
    volatile uint32_t CFG;
    volatile uint32_t STCALIB;
    volatile uint32_t PSCK;
    volatile uint32_t AHBRST;
    volatile uint32_t APB1RST;
    volatile uint32_t APB2RST;
    volatile uint32_t AHBEN;
    volatile uint32_t APB1EN;
    volatile uint32_t APB2EN;
    volatile uint32_t AHBSL;
    volatile uint32_t APB1SL;
    volatile uint32_t APB2SL;
    volatile uint32_t AHBDSL;
    volatile uint32_t APB1DSL;
    volatile uint32_t APB2DSL;
    volatile uint32_t BLECFG;
}reg_rcc_t;

enum RCC_REG_CK_FIELD
{
    RCC_HSI_EN_MASK = 0x1,
    RCC_HSI_EN_POS = 0,
    RCC_HSE_EN_MASK = 0x2,
    RCC_HSE_EN_POS = 1,
    RCC_LSI_EN_MASK = 0x4,
    RCC_LSI_EN_POS = 2,
    RCC_LSE_EN_MASK = 0x8,
    RCC_LSE_EN_POS = 3,
    RCC_PLL0_EN_MASK = 0x10,
    RCC_PLL0_EN_POS = 4,
    RCC_CSS_EN_MASK = 0x80,
    RCC_CSS_EN_POS = 7,
    RCC_LPTIM_LSI_CKEN_MASK = 0x10,
    RCC_LPTIM_LSI_CKEN_POS = 8,
    RCC_LPTIM_LSE_CKEN_MASK = 0x20,
    RCC_LPTIM_LSE_CKEN_POS = 9,
    RCC_LPTIM_PCLK_CKEN_MASK = 0x40,
    RCC_LPTIM_PCLK_CKEN_POS = 10,
    RCC_HSI_RDY_MASK = 0x10000,
    RCC_HSI_RDY_POS = 16,
    RCC_HSE_RDY_MASK = 0x20000,
    RCC_HSE_RDY_POS = 17,
    RCC_LSI_RDY_MASK = 0x40000,
    RCC_LSI_RDY_POS = 18,
    RCC_LSE_RDY_MASK = 0x80000,
    RCC_LSE_RDY_POS = 19,
    RCC_PLL0_RDY_MASK = 0x100000,
    RCC_PLL0_RDY_POS = 20,
    RCC_CSS_FLAG_MASK = 0x800000,
    RCC_CSS_FLAG_POS = 23,
    RCC_SYSCLK_SW_RDY_MASK = 0x10000000,
    RCC_SYSCLK_SW_RDY_POS = 24,
};

enum RCC_REG_CFG_FIELD
{
    RCC_SYSCLK_SW_MASK = 0x7,
    RCC_SYSCLK_SW_POS = 0,
    RCC_SYSCLK_FBY_MASK = 0x8,
    RCC_SYSCLK_FBY_POS = 3,
    RCC_HCLK_SCAL_MASK = 0xf0,
    RCC_HCLK_SCAL_POS = 4,
    RCC_PCLK_SCAL_MASK = 0x700,
    RCC_PCLK_SCAL_POS = 8,
    RCC_HSE_DIV_MASK = 0x7000,
    RCC_HSE_DIV_POS = 12,
    RCC_SYSCLK_FSEL_MASK = 0x18000,
    RCC_SYSCLK_FSEL_POS = 15,
    RCC_PLL0_MUL_MASK = 0x3e0000,
    RCC_PLL0_MUL_POS = 17,
    RCC_LPTIM_CLKS_MASK = 0xc00000,
    RCC_LPTIM_CLKS_POS = 22,
    RCC_MCO_SW_MASK = 0xf000000,
    RCC_MCO_SW_POS = 24,
    RCC_MCO_SCAL_MASK = 0x70000000,
    RCC_MCO_SCAL_POS = 28,
    RCC_CKCFG_MASK = (int)0x80000000,
    RCC_CKCFG_POS = 31,
};

enum RCC_REG_STCALIB_FIELD
{
    RCC_STCALIB_MASK = 0xffffff,
    RCC_STCALIB_POS = 0,
    RCC_STCALIB_SKEW_MASK = 0x40000000,
    RCC_STCALIB_SKEW_POS = 30,
    RCC_STCALIB_NOREF_MASK = (int)0x80000000,
    RCC_STCALIB_NOREF_POS = 31
};

enum RCC_REG_AHB_FIELD
{    
    RCC_CACHE_MASK = 0x1,
    RCC_CACHE_POS = 0,
    RCC_RTC_MASK = 0x40,
    RCC_RTC_POS = 6,
    RCC_IWDT_MASK = 0x800,
    RCC_IWDT_POS = 11,
    RCC_GPIOA_MASK = 0x10000,
    RCC_GPIOA_POS = 16,
    RCC_GPIOB_MASK = 0x20000,
    RCC_GPIOB_POS = 17,
    RCC_GPIOC_MASK = 0x40000,
    RCC_GPIOC_POS = 18,
    RCC_BROM_MASK = 0x1000000,
    RCC_BROM_POS = 24,
    RCC_SRAM0_MASK = 0x2000000,
    RCC_SRAM0_POS = 25,
    RCC_SRAM1_MASK = 0x4000000,
    RCC_SRAM1_POS = 26,
    RCC_SRAM2_MASK = 0x8000000,
    RCC_SRAM2_POS = 27,
    RCC_PWR2_MASK = 0x10000000,
    RCC_PWR2_POS = 28,
    RCC_PWR3_MASK = 0x20000000,
    RCC_PWR3_POS = 29,
};

enum RCC_REG_APB1_FIELD
{
    RCC_GPTIMA1_MASK = 0x1,
    RCC_GPTIMA1_POS = 0,
    RCC_GPTIMB1_MASK = 0x2,
    RCC_GPTIMB1_POS = 1,
    RCC_BSTIM1_MASK = 0x10,
    RCC_BSTIM1_POS = 4,
    RCC_TRNG_MASK =  0x80,
    RCC_TRNG_POS = 7,
    RCC_ECC_MASK = 0x100,
    RCC_ECC_POS = 8,
    RCC_CALC_MASK = 0x200,
    RCC_CALC_POS = 9,
    RCC_CRYPT_MASK = 0x400,
    RCC_CRYPT_POS = 10,
    RCC_WWDG_MASK = 0x800,
    RCC_WWDG_POS = 11,
    RCC_SPI2_MASK = 0x4000,
    RCC_SPI2_POS = 14,
    RCC_UART2_MASK = 0x20000,
    RCC_UART2_POS = 17,
    RCC_UART3_MASK = 0x40000,
    RCC_UART3_POS = 18,
    RCC_I2C1_MASK = 0x200000,
    RCC_I2C1_POS = 21,
    RCC_I2C2_MASK = 0x400000,
    RCC_I2C2_POS = 22,
    RCC_PDM_MASK = 0x4000000,
    RCC_PDM_POS = 26,
    RCC_RF_MASK = 0x20000000,
    RCC_RF_POS = 29,
    RCC_MDM2_MASK = 0x40000000,
    RCC_MDM2_POS = 30,
};

enum RCC_REG_APB2_FIELD
{
    RCC_LPTIM_MASK = 0x1,
    RCC_LPTIM_POS = 0,
    RCC_DMA1_MASK = 0x10,
    RCC_DMA1_POS = 4,
    RCC_ADC_MASK = 0x200,
    RCC_ADC_POS = 9,
    RCC_ADTIM1_MASK = 0x800,
    RCC_ADTIM1_POS = 11,
    RCC_SPI1_MASK = 0x1000,
    RCC_SPI1_POS = 12,
    RCC_UART1_MASK = 0x4000,
    RCC_UART1_POS = 14,
    RCC_GPTIMC1_MASK = 0x10000,
    RCC_GPTIMC1_POS = 16,
    RCC_PIS_MASK = 0x800000,
    RCC_PIS_POS = 23,
    RCC_QSPI_MASK = 0x10000000,
    RCC_QSPI_POS = 28,
    RCC_APB_CACHE_MASK = 0x20000000,
    RCC_APB_CACHE_POS = 29,
};

enum RCC_REG_BLECFG_FIELD
{
    RCC_BLE_CK_SEL_MASK = 0x3,
    RCC_BLE_CK_SEL_POS = 0,
    RCC_BLE_LCK_SEL_MASK = 0x4,
    RCC_BLE_LCK_SEL_POS = 2,
    RCC_BLE_AHBEN_MASK = 0x8,
    RCC_BLE_AHBEN_POS = 3,
    RCC_BLE_MRST_MASK = 0x10,
    RCC_BLE_MRST_POS = 4,
    RCC_BLE_CRYPT_RST_MASK = 0x20,
    RCC_BLE_CRYPT_RST_POS = 5,
    RCC_BLE_LCK_RST_MASK = 0x40,
    RCC_BLE_LCK_RST_POS = 6,
    RCC_BLE_AHB_RST_MASK = 0x80,
    RCC_BLE_AHB_RST_POS = 7,
    RCC_BLE_WKUP_RST_MASK = 0x100,
    RCC_BLE_WKUP_RST_POS = 8,
    RCC_BLE_LPWR_CKEN_MASK = 0x200,
    RCC_BLE_LPWR_CKEN_POS = 9,
    RCC_BLE_MDM_REFCLK_CKEN_MASK = 0x400,
    RCC_BLE_MDM_REFCLK_CKEN_POS = 10,
};

#ifdef __cplusplus
}
#endif

#endif
